SAM3N TC0

Timer Counter (TC0) User Interface

Registers

Register Mapping
Address Register Name Access Reset
0x40010000 Channel Control Register (channel = 0) TC0_CCR0 write-only -
0x40010004 Channel Mode Register (channel = 0) TC0_CMR0 read-write 0x00000000
0x40010008 Stepper Motor Mode Register (channel = 0) TC0_SMMR0 read-write 0x00000000
0x40010010 Counter Value (channel = 0) TC0_CV0 read-only 0x00000000
0x40010014 Register A (channel = 0) TC0_RA0 read-write 0x00000000
0x40010018 Register B (channel = 0) TC0_RB0 read-write 0x00000000
0x4001001C Register C (channel = 0) TC0_RC0 read-write 0x00000000
0x40010020 Status Register (channel = 0) TC0_SR0 read-only 0x00000000
0x40010024 Interrupt Enable Register (channel = 0) TC0_IER0 write-only -
0x40010028 Interrupt Disable Register (channel = 0) TC0_IDR0 write-only -
0x4001002C Interrupt Mask Register (channel = 0) TC0_IMR0 read-only 0x00000000
0x40010040 Channel Control Register (channel = 1) TC0_CCR1 write-only -
0x40010044 Channel Mode Register (channel = 1) TC0_CMR1 read-write 0x00000000
0x40010048 Stepper Motor Mode Register (channel = 1) TC0_SMMR1 read-write 0x00000000
0x40010050 Counter Value (channel = 1) TC0_CV1 read-only 0x00000000
0x40010054 Register A (channel = 1) TC0_RA1 read-write 0x00000000
0x40010058 Register B (channel = 1) TC0_RB1 read-write 0x00000000
0x4001005C Register C (channel = 1) TC0_RC1 read-write 0x00000000
0x40010060 Status Register (channel = 1) TC0_SR1 read-only 0x00000000
0x40010064 Interrupt Enable Register (channel = 1) TC0_IER1 write-only -
0x40010068 Interrupt Disable Register (channel = 1) TC0_IDR1 write-only -
0x4001006C Interrupt Mask Register (channel = 1) TC0_IMR1 read-only 0x00000000
0x40010080 Channel Control Register (channel = 2) TC0_CCR2 write-only -
0x40010084 Channel Mode Register (channel = 2) TC0_CMR2 read-write 0x00000000
0x40010088 Stepper Motor Mode Register (channel = 2) TC0_SMMR2 read-write 0x00000000
0x40010090 Counter Value (channel = 2) TC0_CV2 read-only 0x00000000
0x40010094 Register A (channel = 2) TC0_RA2 read-write 0x00000000
0x40010098 Register B (channel = 2) TC0_RB2 read-write 0x00000000
0x4001009C Register C (channel = 2) TC0_RC2 read-write 0x00000000
0x400100A0 Status Register (channel = 2) TC0_SR2 read-only 0x00000000
0x400100A4 Interrupt Enable Register (channel = 2) TC0_IER2 write-only -
0x400100A8 Interrupt Disable Register (channel = 2) TC0_IDR2 write-only -
0x400100AC Interrupt Mask Register (channel = 2) TC0_IMR2 read-only 0x00000000
0x400100C0 Block Control Register TC0_BCR write-only -
0x400100C4 Block Mode Register TC0_BMR read-write 0x00000000
0x400100C8 QDEC Interrupt Enable Register TC0_QIER write-only -
0x400100CC QDEC Interrupt Disable Register TC0_QIDR write-only -
0x400100D0 QDEC Interrupt Mask Register TC0_QIMR read-only 0x00000000
0x400100D4 QDEC Interrupt Status Register TC0_QISR read-only 0x00000000
0x400100E4 Write Protect Mode Register TC0_WPMR read-write 0x00000000

Register Fields

TC0 Channel Control Register (channel = 0)

Name: TC0_CCR0

Access: write-only

Address: 0x40010000

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SWTRG CLKDIS CLKEN

TC0 Channel Mode Register (channel = 0)

Name: TC0_CMR0

Access: read-write

Address: 0x40010004

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS

Alternate: WAVE_EQ_1

31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS

TC0 Stepper Motor Mode Register (channel = 0)

Name: TC0_SMMR0

Access: read-write

Address: 0x40010008

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DOWN GCEN

TC0 Counter Value (channel = 0)

Name: TC0_CV0

Access: read-only

Address: 0x40010010

31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV

TC0 Register A (channel = 0)

Name: TC0_RA0

Access: read-write

Address: 0x40010014

31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA

TC0 Register B (channel = 0)

Name: TC0_RB0

Access: read-write

Address: 0x40010018

31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB

TC0 Register C (channel = 0)

Name: TC0_RC0

Access: read-write

Address: 0x4001001C

31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC

TC0 Status Register (channel = 0)

Name: TC0_SR0

Access: read-only

Address: 0x40010020

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Enable Register (channel = 0)

Name: TC0_IER0

Access: write-only

Address: 0x40010024

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Disable Register (channel = 0)

Name: TC0_IDR0

Access: write-only

Address: 0x40010028

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Mask Register (channel = 0)

Name: TC0_IMR0

Access: read-only

Address: 0x4001002C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Channel Control Register (channel = 1)

Name: TC0_CCR1

Access: write-only

Address: 0x40010040

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SWTRG CLKDIS CLKEN

TC0 Channel Mode Register (channel = 1)

Name: TC0_CMR1

Access: read-write

Address: 0x40010044

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS

Alternate: WAVE_EQ_1

31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS

TC0 Stepper Motor Mode Register (channel = 1)

Name: TC0_SMMR1

Access: read-write

Address: 0x40010048

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DOWN GCEN

TC0 Counter Value (channel = 1)

Name: TC0_CV1

Access: read-only

Address: 0x40010050

31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV

TC0 Register A (channel = 1)

Name: TC0_RA1

Access: read-write

Address: 0x40010054

31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA

TC0 Register B (channel = 1)

Name: TC0_RB1

Access: read-write

Address: 0x40010058

31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB

TC0 Register C (channel = 1)

Name: TC0_RC1

Access: read-write

Address: 0x4001005C

31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC

TC0 Status Register (channel = 1)

Name: TC0_SR1

Access: read-only

Address: 0x40010060

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Enable Register (channel = 1)

Name: TC0_IER1

Access: write-only

Address: 0x40010064

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Disable Register (channel = 1)

Name: TC0_IDR1

Access: write-only

Address: 0x40010068

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Mask Register (channel = 1)

Name: TC0_IMR1

Access: read-only

Address: 0x4001006C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Channel Control Register (channel = 2)

Name: TC0_CCR2

Access: write-only

Address: 0x40010080

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SWTRG CLKDIS CLKEN

TC0 Channel Mode Register (channel = 2)

Name: TC0_CMR2

Access: read-write

Address: 0x40010084

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS

Alternate: WAVE_EQ_1

31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS

TC0 Stepper Motor Mode Register (channel = 2)

Name: TC0_SMMR2

Access: read-write

Address: 0x40010088

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - DOWN GCEN

TC0 Counter Value (channel = 2)

Name: TC0_CV2

Access: read-only

Address: 0x40010090

31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
7 6 5 4 3 2 1 0
CV

TC0 Register A (channel = 2)

Name: TC0_RA2

Access: read-write

Address: 0x40010094

31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
7 6 5 4 3 2 1 0
RA

TC0 Register B (channel = 2)

Name: TC0_RB2

Access: read-write

Address: 0x40010098

31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
7 6 5 4 3 2 1 0
RB

TC0 Register C (channel = 2)

Name: TC0_RC2

Access: read-write

Address: 0x4001009C

31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
7 6 5 4 3 2 1 0
RC

TC0 Status Register (channel = 2)

Name: TC0_SR2

Access: read-only

Address: 0x400100A0

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Enable Register (channel = 2)

Name: TC0_IER2

Access: write-only

Address: 0x400100A4

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Disable Register (channel = 2)

Name: TC0_IDR2

Access: write-only

Address: 0x400100A8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Interrupt Mask Register (channel = 2)

Name: TC0_IMR2

Access: read-only

Address: 0x400100AC

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC0 Block Control Register

Name: TC0_BCR

Access: write-only

Address: 0x400100C0

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - SYNC

TC0 Block Mode Register

Name: TC0_BMR

Access: read-write

Address: 0x400100C4

31 30 29 28 27 26 25 24
- - - - - - MAXFILT
23 22 21 20 19 18 17 16
MAXFILT FILTER - IDXPHB SWAP
15 14 13 12 11 10 9 8
INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN
7 6 5 4 3 2 1 0
- - TC2XC2S TC1XC1S TC0XC0S

TC0 QDEC Interrupt Enable Register

Name: TC0_QIER

Access: write-only

Address: 0x400100C8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC0 QDEC Interrupt Disable Register

Name: TC0_QIDR

Access: write-only

Address: 0x400100CC

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC0 QDEC Interrupt Mask Register

Name: TC0_QIMR

Access: read-only

Address: 0x400100D0

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC0 QDEC Interrupt Status Register

Name: TC0_QISR

Access: read-only

Address: 0x400100D4

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - DIR
7 6 5 4 3 2 1 0
- - - - - QERR DIRCHG IDX

TC0 Write Protect Mode Register

Name: TC0_WPMR

Access: read-write

Address: 0x400100E4

31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7 6 5 4 3 2 1 0
- - - - - - - WPEN